Standard Number: JEDEC JESD61A-2007
Title: isothermal electromigration test procedure
Publication Date: 2007/5/1
Execute Date: 2007/5/1
Publisher: Joint Electron Device Engineering Council(JEDEC)
Number of Pages:50
Description:As the copper damascene technology has gained widespread use for ULSI interconnections, a renewed
interest has developed in fast wafer level reliability (WLR) measurements to evaluate electromigration.
The standard package level reliability (PLR) tests, used in the semiconductor industry, are very expensive
when applied to copper metallizations, in comparison with aluminum-based structures, due to the
considerable cost of the high temperature environmental chambers required (a typical stress temperature
is 350 °C) and to the time (weeks, months) required to perform some characterizations.
: PDF(Acrobat Reader) or Word version doc
Tile in English: isothermal electromigration test procedure